1. Field of the Invention
The present invention relates to a switching power supply circuit and an overcurrent protection method for the switching power supply circuit, and particularly relates to a switching power supply circuit and an overcurrent protection method for the switching power supply circuit whereby reliable protection is provided against breakdown of circuit elements and the like due to overcurrent.
2. Description of the Related Art
FIG. 9 is a circuit diagram depicting an example of a conventional switching power supply circuit. The switching circuit depicted in FIG. 9 constitutes a step-down DC-DC converter. In this switching circuit, a field-effect transistor (hereinafter referred to simply as “transistor”) 20 is used as a switching element. A direct current outputted from an input power supply 10 is stepped down by controlling the on/off state of the transistor 20 by means of a drive pulse DP′ from a control circuit 100, and the stepped-down current is rectified by a rectifier circuit made up of an inductor 30 and diode 40. This rectified current is outputted from an output terminal 50.
In this conventional switching power supply circuit, a capacitor 60 smoothes the direct current voltage outputted from the output terminal 50, resistors 70 and 80 divide and detect the direct current voltage outputted from the output terminal 50, and the voltage detected by the resistors 70 and 80 is applied to the control circuit 100 as a feedback signal FB.
The control circuit 100 comprises a PWM (Pulse Width Modulation) circuit 110 and an overcurrent protection circuit 120. The PWM circuit 110 generates a drive pulse DP (PWM pulse) in synchronism with a clock pulse CK at a prescribed period for controlling the on/off state of the transistor 20 based on a feedback signal FB.
The overcurrent protection circuit 120 continually monitors the current I-H flowing through the transistor 20. When the current I-H flowing through the transistor 20 exceeds a pre-set prescribed value, the overcurrent protection circuit 120 operates so as to mask the drive pulse DP outputted from the PWM circuit 110 and turn the transistor 20 off.
In FIG. 9, I-L indicates a flywheel current that flows through diode 40 and inductor 30 when the transistor 20 is turned off.
FIG. 10 is a circuit diagram depicting an example of the overcurrent protection circuit 120 of the switching power supply circuit depicted in FIG. 9; FIG. 11 is a circuit diagram depicting an example of the overcurrent detection circuit 121 depicted in FIG. 10; and FIG. 12 is a timing chart depicting the operation of the circuits depicted in FIGS. 9 through 11.
In FIG. 11, the current I-H flowing through the transistor 20 is detected by the circuit that includes the resistor R1 and transistor FET1.
In FIG. 11, the transistor 20 and transistor FET1 constitute a current mirror circuit. From the terminal T2, the drive pulse DP′ for controlling the on/off state of the transistor 20 is applied to the gates of both the transistor 20 and the transistor FET1, and a current (I-H)/n, which is the 1/nth of the current I-H flowing through the transistor 20, flows into the resistor R1.
Consequently, a detected voltage VId that corresponds to the current I-H flowing through the transistor 20 can be obtained from the junction of the resistor R1 with the transistor FET1.
This detected voltage VId is applied to a comparator CO, and with the aid of the comparator CO, the detected voltage VId is compared with the voltage (Vin−V1) obtained by subtracting from the voltage Vin of the input power supply 10 a prescribed reference voltage V1 for detecting overcurrent (see FIG. 12A).
When the detected voltage VId becomes smaller than the voltage (Vin−V1), specifically, when the current I-H flowing through the transistor 20 increases above a prescribed value, an overcurrent detection signal OCD is outputted from the comparator CO (see FIG. 12B).
This overcurrent detection signal OCD is usually low-level, as depicted in FIG. 12B. However, it becomes high-level when the current I-H flowing through the transistor 20 exceeds a prescribed value.
The overcurrent detection signal OCD outputted from the overcurrent detection circuit 121 is outputted from the terminal T1 depicted in FIG. 11 and applied to the set terminal S of the flip-flop 123 depicted in FIG. 10.
The clock signal CK from the terminal 122 used by the PWM circuit 110 is applied to the reset terminal R of the flip-flop 123, which goes to “high-level” when the overcurrent detection signal OCD from the inverted output terminal thereof is “low-level,” and generates a low-level gate signal GS when the overcurrent detection signal OCD goes to “high-level” (see FIG. 12E). This gate signal GS is applied to an AND circuit 125.
A drive pulse DP (see FIG. 12D) outputted from the PWM circuit 110 is applied from the terminal 124 to the other input terminal in the AND circuit 125. As a result, when the overcurrent detection signal OCD is brought to a “high-level”, the AND circuit 125 masks the drive pulse DP outputted from the PWM circuit 110. In other words, the AND circuit 125 prohibits outputting of the drive pulse DP from the PWM circuit 110 (see FIG. 12F).
The output of the AND circuit 125 is inverted by an inverter 126 and is outputted from a terminal 127 as a drive pulse DP′ for controlling the on/off state of the transistor 20 (see FIG. 12G).
Also, the time period Tocp depicted in FIG. 12E consists of the operating period of the overcurrent protection circuit 120.
Also, in the above-mentioned circuit example, because a P channel MOS is used as the transistor 20, the transistor 20 is turned on when the drive pulse DP′ is “low-level.”
The above-mentioned overcurrent protection circuit 120 also has such problems as are depicted in FIG. 13.
Specifically, the minimum duty in the drive pulse DP′ for controlling the on/off state of the transistor 20 is determined from the performance limit of the circuit. Therefore, as depicted in FIG. 13E, the minimum value of the on-duty time wherein the drive pulse DP′ can be maintained at low-level is restricted to Tmin.
Because of this, as depicted in FIG. 13F, for example, even if the output voltage goes to zero due to load shorting and the like and the current I-H flowing through the transistor 20 exceeds the pre-set prescribed value Vocp (see FIG. 13A), the transistor 20 does not immediately turn off during the minimum duty time Tmin. The current I-H also rises abruptly when the current I-H exceeds the saturation current Isa of the inductor 30.
At the time when the next clock signal CK rises while the overcurrent protection circuit 120 is in operation, if the flywheel current I-L is not sufficiently attenuated as depicted by the dash line in FIG. 13A, current superposition occurs in the inductor 30 (see FIG. 13A). As a result of these facts, the circuit can break down in a worst case.
These facts are likely to occur in such an occasion where the frequency of the clock signal CK is set high, i.e., at a few MHz and the load is extremely large.
Techniques for overcoming the problems caused by the above-mentioned current superposition have been disclosed in Japanese Patent Application Publication Nos. 07-46828 and 11-341791, and in U.S. Pat. No. 5,808,455.
To prevent operating lag in the overcurrent protection circuit in cases in which the switching frequency is high, the switching power supply circuit disclosed in Japanese Patent Application Publication No. 07-46828 is configured so as to minimize the effects of lag time between the time an overcurrent state is detected and the time the transistor turns off, by lowering the switching frequency when the output voltage falls to a prescribed level.
The switching power supply circuit disclosed in Japanese Patent Application Publication No. 11-341791 is configured to perform control so as to lower the detection level of the overcurrent when the output voltage further declines due to a short-circuit or the like, in addition to having the configuration of the switching power supply circuit disclosed in Japanese Patent Application Publication No. 07-46828.
The switching power supply circuit disclosed in U.S. Pat. No. 5,808,455 focuses on the problems of the conventional configuration depicted in FIG. 1 of the same reference, specifically, the problem of power dissipation in a conventional configuration in which a current detecting resistor R is connected in series with an inductor L, and provides a configuration whereby overcurrent can be detected while minimizing power dissipation by disposing a current detection resistor R on the low side as depicted in FIG. 2 of the same reference. As depicted in FIG. 3 of the same reference, this technique is furthermore designed to effectively restrict overcurrent and minimize breakdown in circuit elements by extending the electrical discharge cycle until the inductor current IL reaches I LIMIT 2 after the inductor current IL exceeds a prescribed reference value I LIMIT 1. Also, these two reference values are set and compared using a Schmitt trigger U1.
A configuration whereby a pre-set timer circuit is started upon detection of overcurrent by the overcurrent detection circuit and the drive pulse for controlling the switching on and off of the switching power supply circuit is masked during the timer circuit period has also been considered as another technique for overcoming the problems of the above-mentioned current superposition.
The above-mentioned current superposition can also be prevented and circuit damage due to overcurrent can be prevented in this configuration if the timer circuit period is set sufficiently long.
However, both of the switching power supply circuits disclosed in the above-mentioned Japanese Patent Application Laid-open Nos. H7-46828 and H11-341791 have the problem of reduced responsiveness, because they reduce the switching frequency when overcurrent is detected, and a configuration that uses a timer circuit has problems whereby the timing period of the timer circuit is difficult to set, and the switching cycle of the switching power supply circuit is effectively lengthened, yielding inadequate performance if the set timing period is too long.
Also, in a configuration that uses a timer circuit, the user does not usually know the saturation current value of the inductor of the switching power supply circuit being used. Therefore, the above-mentioned timing period of the timer circuit must actually be set quite long to allow a margin, in which case problems such as follows may be encountered.    1) Startup time is lengthened, and    2) Response to sudden load fluctuations is delayed
Also, because overcurrent detection is delayed by having the overcurrent detection resistor R disposed on the low side, and because both a positive power supply and negative power supply are needed in order to utilize a Schmitt trigger U1 provided with two reference values in a configuration in which the overcurrent detection resistor R is disposed on the low side, the switching power supply circuit disclosed in U.S. Pat. No. 5,808,455 has many aspects that demand improvement in order to obtain a simple circuit structure.